The ReTiS lab was at EMBEDDED SYSTEMS WEEK 2019 #esweek2019, and the following presentations have been delivered by researchers from the lab. Conference: #CASES, Session: Interconnect Design 𝐈𝐬 𝐘𝐨𝐮𝐫 𝐁𝐮𝐬 𝐀𝐫𝐛𝐢𝐭𝐞𝐫 𝐑𝐞𝐚𝐥𝐥𝐲 𝐅𝐚𝐢𝐫? 𝐑𝐞𝐬𝐭𝐨𝐫𝐢𝐧𝐠 𝐅𝐚𝐢𝐫𝐧𝐞𝐬𝐬 𝐢𝐧 𝐀𝐗𝐈 𝐈𝐧𝐭𝐞𝐫𝐜𝐨𝐧𝐧𝐞𝐜𝐭𝐬 𝐟𝐨𝐫 𝐅𝐏𝐆𝐀 𝐒𝐨𝐂𝐬 (#FrancescoRestuccia, Marco Pagani, Alessandro Biondi, Mauro Marinoni, and Giorgio Buttazzo) Conference: #CODES+#ISSS, Session: Adaptive and Intermittent Embedded […]
To recognize the best paper published in the 2018 IEEE Transactions on Industrial Informatics journal, the Editorial Board of the journal selected the article “Modeling and Analysis of Engine Control Tasks Under Dynamic Priority Scheduling” authored by Alessandro Biondi and Giorgio Buttazzo of Sant’Anna TeCIP Institute. Researchers Alessandro Biondi, and Giorgio Buttazzo, working at the TeCIP Institute Real-Time Systems Laboratory […]
The Facebook page of the ReTiS lab is now available. Follow it to stay updated on the new activities!
On 27 September Bright #NotteDeiRicercatori returns to Tuscany. The rich program of the event will involve over 1500 researchers in 350 meetings, events, presentations, and shows in 14 Tuscan cities. The ReTiS lab will present its real-time demos on Friday afternoon at the main building of the Scuola Sant’Anna in Piazza Martiri della Libertà. More […]
The ReTiS Lab is active on many research topics related to several aspects of embedded and cyber-physical systems, support for time-critcal applications, operting systems, and cloud computing. … bla bla bla… Scheduling algorithms Adaptive resource management and optimization Design methods and tools for cyber-physical systems Open source real-time operating systems Operating systems for massively parallel […]
The IEEE Real-Time Systems Symposium (RTSS) is the premier conference in the field of real-time systems, presenting innovations with respect to both theory and practice. RTSS’18 has been held in Nashville, Tennessee, USA, and the ReTiS lab was present with three accepted papers: “Memory Feasibility Analysis of Parallel Tasks Running on Scratchpad-Based Architectures,” Daniel Casini, Alessandro […]
Development of kernel and hypervisor mechanisms for railway systems at the RETIS Lab – Scuola Superiore Sant’Anna. Research objectives The research is part of a larger project funded by RFI, the company that manages the Italian railway infrastructure (http://www.rfi.it/). The large RFI project plans to replace all computing platforms, currently used on trains and in railway stations, with […]
The ReTiS lab frequently needs to involve new smart and motivated people in the team to deal with research, exploitation, and technology transfer.
The ReTiS laboratory partecipates in two Ph.D. degrees.
This is a list of most of the currently available thesis at the ReTiS.