Software architecture for Predictable HEterogeneous REal-time systems
About the project
The SPHERE project aims at providing an integrated operating system framework to abstract the hardware complexity of cutting-edge multi-core platforms and simplify the management of heterogeneous computational resources.
The SPHERE framework addresses these challenges by providing methodologies and tools for:
- analyzing the execution behavior of the applications tasks and predict their average and worst case response times;
- enabling fast and predictable communication mechanisms between multiple computing nodes;
- enforcing security features to guarantee data integrity and nodes confidentiality.
The feasibility of the SPHERE framework will be validated in a highly relevant industrial use case: a pioneering autonomous driving system for the automotive domain.
Duration: 3 years
Start date: 1/09/2019
End date: 31/08/2022
Coordinator: Giorgio Buttazzo (Scuola Sant’Anna)
Funding Body: MIUR – PRIN 2017
Project Description
The SPHERE project will provide an integrated framework to allow an easy programmability of next-generation heterogeneous multi-core systems for developing real-time parallel applications, decreasing by order-of-magnitudes the time-to-market and development cost. To that aim, SPHERE investigates predictable and efficient execution models and co-scheduling mechanisms to manage the parallel computing power of the addressed platform. An open source virtualization layer integrating these mechanisms allows hiding the complex management of heterogeneous resources under a clean parallel programming interface based on a widely adopted programming model.
As shown in the figure, the SPHERE framework considers two kinds of processing devices: normal cores (possibly with different processing power) and special devices, like GPUs, DSP clusters and FPGA fabric. A hypervisor layer residing on the host subsystem will manage the access to all devices in a predictable way, providing a guaranteed bandwidth to each software component. Each component comes with its own operating system and requirements, which shall not be influenced by other components.
The main difficulty in achieving this goal on heterogeneous platforms is due to the mutual interferences that arise on the shared resources like accelerators, I/O devices, communication, and memory resources. To limit such interferences, the hypervisor implements innovative co-scheduling techniques to arbitrate the access to all shared resources, ensuring that the maximum lateness of each running component is predictably bounded.
To guarantee a secure and trusted execution environment, SPHERE extends and integrates the selected hypervisor with innovative features devoted to hardware security and trust.
Concerning communication, SPHERE targets novel network architectures and configurations, bandwidth reservation mechanisms, medium access control techniques, and suitable transmission scheduling algorithms to meet the requirements imposed by the applications under the typical operating conditions.
Partners
Scuola Superiore Sant’Anna
TeCIP – ReTiS
Università degli Studi di Modena e Reggio Emilia
FIM – HiPERT lab
Università di Catania
DIEEI lab
News
July 2023
SPHERE on Springer Real-Time Systems
A paper on the SPHERE project’s topics has been published on the Springer Real-Time Systems.
Cittadini, E., Marinoni, M., Biondi, A. et al. Supporting AI-powered real-time cyber-physical systems on heterogeneous platforms via hypervisor technology. Real-Time Syst (2023). DOI: 10.1007/s11241-023-09402-4.
January 2023
SPHERE on IEEE Transactions on Computers
A paper on the SPHERE project’s topics has been published on the IEEE Transactions on Computers.
M. Zini, D. Casini, and A. Biondi, “Analyzing Arm’s MPAM From the Perspective of Time Predictability,” in IEEE Transactions on Computers, vol. 72, no. 1, pp. 168-182, 1 Jan. 2023, DOI: 10.1109/TC.2022.3202720.
November 2022
SPHERE on IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A paper on the SPHERE project’s topics has been published on the IEEE Computer-Aided Design of Integrated Circuits and Systems transactions.
N. Borgioli, M. Zini, D. Casini, G. Cicero, A. Biondi and G. Buttazzo, “An I/O Virtualization Framework With I/O-Related Memory Contention Control for Real-Time Systems,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 11, pp. 4469-4480, Nov. 2022, DOI: 10.1109/TCAD.2022.3202434.
May 2022
SPHERE on Software: Practice and Experience
A paper on the SPHERE project’s topics has been published on the Software: Practice and Experience journal.
Matteo Zini, Giorgiomaria Cicero, Daniel Casini, and Alessandro Biondi, “Profiling and controlling I/O-related memory contention in COTS heterogeneous platforms,” in Software: Practice and Experience, vol. 52, no. 5, pp. 1095-1113, May 2022, DOI: 10.1002/spe.3053.
May 2021
SPHERE on IEEE Access
A paper on the SPHERE project’s topics has been published on the IEEE Access journal.
A. Biondi et al., “SPHERE: A Multi-SoC Architecture for Next-Generation Cyber-Physical Systems Based on Heterogeneous Platforms,” in IEEE Access, vol. 9, pp. 75446-75459, 2021, DOI: 10.1109/ACCESS.2021.3080842.
18 May 2021 – Nashville (USA)
SPHERE @ RTAS 2021
A paper on the SPHERE project’s topics has been accepted and presented at the 27th Real-Time and Embedded Technology and Applications Symposium (RTAS 2021).
D. Casini, A. Biondi, G. Cicero, and G. Buttazzo, “Latency Analysis of I/O Virtualization Techniques in Hypervisor-Based Real-Time Systems,” 2021 IEEE 27th Real-Time and Embedded Technology and Applications Symposium (RTAS), Nashville, TN, USA, 2021, DOI: 10.1109/RTAS52030.2021.00032.
18 September 2020
Project meeting
Due to COVID-19 restrictions, the third project meeting has been conducted online.
10 September 2020 – Vienna (Austria)
SPHERE @ ETFA 2020
A paper on the SPHERE project’s topics has been accepted and presented at the 25th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA 2020).
Luca Leonardi, Lucia Lo Bello, Gaetano Patti, “Towards Time-Sensitive Networking in Heterogeneous Platforms with Virtualization,” In Proceedings of the 25th IEEE Conference on Emerging Technologies and Factory Automation (ETFA 2020), 8-11 September 2020, Vienna, Austria.
24 July 2020 – San Francisco (USA)
SPHERE @ DAC 2020
A paper on the SPHERE project’s topics has been accepted and presented at the 57th ACM/IEEE Design Automation Conference (DAC 2020).
Francesco Restuccia, Alessandro Biondi, Mauro Marinoni, Giorgiomaria Cicero, and Giorgio Buttazzo, “AXI HyperConnect: A Predictable, Hypervisor-level AXI Interconnect for Hardware Accelerators in FPGA SoC“, In Proceedings of the 57th ACM/IEEE Design Automation Conference (DAC 2020), San Francisco, California, USA, July 19-23, 2020.
21 April 2020 – Sydney (Australia)
SPHERE @ RTAS 2020
A paper on the SPHERE project’s topics has been accepted and presented at the 26th Real-Time and Embedded Technology and Applications Symposium (RTAS 2020).
D. Casini, A. Biondi, G. Nelissen, and G. Buttazzo, “A Holistic Memory Contention Analysis for Parallel Real-Time Tasks under Partitioned Scheduling,” 2020 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), Sydney, NSW, Australia, April 21-24, 2020, DOI: 10.1109/RTAS48715.2020.000-3.
February 2020
SPHERE on IEEE Access
A paper on the SPHERE project’s topics has been published on the IEEE Access journal.
R. Martino and A. Cilardo, “SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey“, in IEEE Access, vol. 8, pp. 28415-28436, 2020, DOI: 10.1109/ACCESS.2020.2972265.
23 January 2020 – Modena (Italy)
Project meeting
The HiPeRT Lab held the second meeting of the SPHERE project.
30 September 2019 – Naples (Italy)
SPHERE @ IWES 2019
The SPHERE project will be presented at the 4th Italian Workshop on Embedded Systems in Naples (September 30 – October 1, 2019).
9 September 2019 – Pisa (Italy)
Kick-off meeting
The ReTiS lab held the kick-off meeting of the SPHERE project.