Embedded System Week 2019
The ReTiS lab was at Embedded Systems Week 2019 (ESWeek2019), and researchers from the lab have delivered the following presentations. Conference: CASES, Session: Interconnect Design “Is Your Bus Arbiter Really Fair? Restoring Fairness in AXI Interconnect for FPGA SoCs” – Francesco Restuccia, Marco Pagani, Alessandro Biondi, Mauro Marinoni, and Giorgio Buttazzo Conference: CODES+ISSS, Session: Adaptive and Intermittent Embedded […]