We are honored to announce that the paper “Time-Predictable Acceleration of Deep Neural Networks on FPGA SoCs with Multi-Core DPUs” has received the Outstanding Paper Award at the 32nd IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2026), one of the premier conferences in the field of real-time embedded systems, organized in Saint-Malo (France) by the IEEE TCRTS (Technical Community on Real-Time Systems).
The paper was authored by Federico Aromolo, Niko Salamini, Jacopo Del Granchio, Alessandro Biondi, Mauro Marinoni, and Giorgio Buttazzo (Scuola Superiore Sant’Anna).
The article addresses a key challenge in deploying artificial intelligence within safety-critical cyber-physical systems: ensuring that deep neural networks can execute within strict and predictable timing constraints. Applications such as autonomous vehicles, industrial robotics, and medical devices increasingly rely on neural networks for perception and decision-making; however, guaranteeing that these computations meet hard real-time deadlines remains extremely challenging, particularly under concurrent execution of multiple AI workloads.
In this context, hardware acceleration is essential to achieve both the performance and predictability required by such systems. General-purpose Graphics Processing Units (GPUs) provide high computational throughput for AI workloads, but their performance is difficult to predict due to dynamic scheduling, caching effects, and contention for shared resources, making them less suitable for hard real-time guarantees.
The proposed framework enables time-predictable execution of deep neural networks on Field-Programmable Gate Array (FPGA)-based platforms, where Deep Learning Processing Units (DPUs) are deployed as dedicated hardware accelerators for neural network inference. By combining memory traffic regulation with advanced real-time scheduling techniques, the approach provides formal timing guarantees while maintaining high computational efficiency and low power consumption.
The work demonstrates that multi-core DPU-based architectures can deliver both high-performance AI inference and the temporal predictability required by mission-critical real-time systems. Overall, the proposed techniques support the integration of artificial intelligence into next-generation automotive, industrial, robotics, and aerospace applications, where reliability, timing guarantees, and energy efficiency are essential.