Francesco Restuccia
Ph.D. student from October 2017 to October 2020. Postdoctoral researcher from October 2020 to October 2022.
Publications
Search:
Year:
- YEAR: 2022
-
Restuccia, F.; Pagani, M.; Mascitti, A.; Barrow, M.; Marinoni, M.; Biondi, A.; Buttazzo, G.; Kastner, R.
ARTe: Providing real-time multitasking to Arduino
32767 - 0 THE JOURNAL OF SYSTEMS AND SOFTWARE (2022)
Volume nr. :127
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Serra, G.; Fara, P.; Cicero, G.; Restuccia, F.; Biondi, A.
PAC-PL: Enabling Control-Flow Integrity with Pointer Authentication in FPGA SoC Platforms
241 - 253 2022 IEEE 28th Real-Time and Embedded Technology and Applications Symposium (RTAS) - IEEE (2022)
Volume nr. :127
- YEAR: 2021
-
Restuccia, F.; Biondi, A.
Time-Predictable Acceleration of Deep Neural Networks on FPGA SoC Platforms
441 - 454 Proceedings - Real-Time Systems Symposium - Institute of Electrical and Electronics Engineers Inc. (2021)
Volume nr. :127
- YEAR: 2020
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Restuccia, Francesco; Biondi, Alessandro; Marinoni, Mauro; Buttazzo, Giorgio
Safely Preventing Unbounded Delays During Bus Transactions in FPGA-based SoC
129 - 137 2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) - IEEE (2020)
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Restuccia, F.; Biondi, A.; Marinoni, M.; Cicero, G.; Buttazzo, G.
AXI HyperConnect: A predictable, hypervisor-level interconnect for hardware accelerators in FPGA SoC
1 - 6 Proceedings - Design Automation Conference - Institute of Electrical and Electronics Engineers Inc. (2020)
Volume nr. :127
-
Restuccia, F.; Pagani, M.; Biondi, A.; Marinoni, M.; Buttazzo, G.
Modeling and analysis of bus contention for hardware accelerators in FPGA SoCs
Leibniz International Proceedings in Informatics, LIPIcs - Schloss Dagstuhl- Leibniz-Zentrum fur Informatik GmbH, Dagstuhl Publishing (2020)
Volume nr. :127
- YEAR: 2019
-
Restuccia, Francesco; Pagani, M.; Biondi, A.; Marinoni, M.; Buttazzo, G.
Is your bus arbiter really fair? Restoring fairness in axi interconnects for FPGA SOCs
1 - 22 ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS (2019)
Volume nr. :18
Issue nr. :5
- YEAR: 2022
-
Restuccia, F.; Pagani, M.; Mascitti, A.; Barrow, M.; Marinoni, M.; Biondi, A.; Buttazzo, G.; Kastner, R.
ARTe: Providing real-time multitasking to Arduino
32767 - 0 THE JOURNAL OF SYSTEMS AND SOFTWARE (2022)
Volume nr. :127
- YEAR: 2019
-
Restuccia, Francesco; Pagani, M.; Biondi, A.; Marinoni, M.; Buttazzo, G.
Is your bus arbiter really fair? Restoring fairness in axi interconnects for FPGA SOCs
1 - 22 ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS (2019)
Volume nr. :18
Issue nr. :5
- YEAR: 2022
-
Serra, G.; Fara, P.; Cicero, G.; Restuccia, F.; Biondi, A.
PAC-PL: Enabling Control-Flow Integrity with Pointer Authentication in FPGA SoC Platforms
241 - 253 2022 IEEE 28th Real-Time and Embedded Technology and Applications Symposium (RTAS) - IEEE (2022)
Volume nr. :127
- YEAR: 2021
-
Restuccia, F.; Biondi, A.
Time-Predictable Acceleration of Deep Neural Networks on FPGA SoC Platforms
441 - 454 Proceedings - Real-Time Systems Symposium - Institute of Electrical and Electronics Engineers Inc. (2021)
Volume nr. :127
- YEAR: 2020
-
Restuccia, Francesco; Biondi, Alessandro; Marinoni, Mauro; Buttazzo, Giorgio
Safely Preventing Unbounded Delays During Bus Transactions in FPGA-based SoC
129 - 137 2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) - IEEE (2020)
-
Restuccia, F.; Biondi, A.; Marinoni, M.; Cicero, G.; Buttazzo, G.
AXI HyperConnect: A predictable, hypervisor-level interconnect for hardware accelerators in FPGA SoC
1 - 6 Proceedings - Design Automation Conference - Institute of Electrical and Electronics Engineers Inc. (2020)
Volume nr. :127
-
Restuccia, F.; Pagani, M.; Biondi, A.; Marinoni, M.; Buttazzo, G.
Modeling and analysis of bus contention for hardware accelerators in FPGA SoCs
Leibniz International Proceedings in Informatics, LIPIcs - Schloss Dagstuhl- Leibniz-Zentrum fur Informatik GmbH, Dagstuhl Publishing (2020)
Volume nr. :127