Embedded System Week 2019

The ReTiS lab was at EMBEDDED SYSTEMS WEEK 2019 #esweek2019, and the following presentations have been delivered by researchers from the lab. Conference: #CASES, Session: Interconnect Design 𝐈𝐬 𝐘𝐨𝐮𝐫 𝐁𝐮𝐬 𝐀𝐫𝐛𝐢𝐭𝐞𝐫 𝐑𝐞𝐚𝐥𝐥𝐲 𝐅𝐚𝐢𝐫? 𝐑𝐞𝐬𝐭𝐨𝐫𝐢𝐧𝐠 𝐅𝐚𝐢𝐫𝐧𝐞𝐬𝐬 𝐢𝐧 𝐀𝐗𝐈 𝐈𝐧𝐭𝐞𝐫𝐜𝐨𝐧𝐧𝐞𝐜𝐭𝐬 𝐟𝐨𝐫 𝐅𝐏𝐆𝐀 𝐒𝐨𝐂𝐬 (#FrancescoRestuccia, Marco Pagani, Alessandro Biondi, Mauro Marinoni, and Giorgio Buttazzo) Conference: #CODES+#ISSS, Session: Adaptive and Intermittent Embedded […]